Referring to FIG. 1, a conventional memory device includes a memory cell block 10, a plurality of bit lines 11 coupled to the memory cell block 10, and a plurality of word lines 12 coupled to the memory cell block 10.
The memory cell block 10 includes a plurality of memory cells 13 arranged in a matrix. The word lines 12 transmit a control input to the memory cells 13 in order to control the memory cells 13 to output data stored therein to the bit lines 11.
As the demand for storage capacity of memory devices increases, memory cell blocks 10 with many more memory cells 13 would be preferable. However, to accommodate this, each bit line 11 is made longer to be coupled to more memory cells 13, which inevitably increases a capacitance seen thereat.
Because of the relatively large capacitance seen at each bit line 11, voltages outputted by the memory cells 13 may not promptly propagate to the bit lines 11 (i.e., the memory cells 13 may not be able to drive the bit lines 11 efficiently). As a result, a plurality of sense amplifiers 14 are employed to be coupled respectively to the bit lines 11 to assist in amplifying voltages on the bit lines 11 in order to facilitate data transmission and allow the memory device to operate at a higher frequency.
Nonetheless, the sense amplifiers 14 may be undesirable components of the memory device due to their relatively large power consumption. Therefore, it may be beneficial to attempt to address the issue of the capacitance seen at each bit line 11, and to omit the sense amplifiers 14 altogether.
Referring to FIG. 2, alternatively, a plurality of memory cell blocks may be combined in a memory device and controlled together, such that control logic for the same can be simplified to save area. For example, the memory device includes four memory cell blocks, one-hundred-and-twenty-eight bit lines (bit0_bk0 to bit31_bk3) and two-hundred-and-fifty-six word lines (ctr_0 to ctr_255). Each memory cell block includes two-hundred-and-fifty-six by thirty-two memory cells (MCs) 13 that are arranged in a matrix with two-hundred-and-fifty-six rows and thirty-two columns, and that are controlled via the word lines (ctr_0 to ctr_255) to output data stored therein to the bit lines (bit0_bkA to bit31_bkA), where 0≦A≦3. Moreover, thirty-two multiplexers (MUXs) 15 are employed to output voltages at the bit lines (bit0_bk0 to bit31_bk3) to thirty-two output lines (bit0 to bit31). Preferably, the columns of the memory cells 13 of the memory cell blocks are arranged in the order of the first column of the first memory cell block, the first column of the second memory cell block, the first column of the third memory cell block, the first column of the fourth memory cell block, the second column of the first memory cell block, the second column of the second memory cell block and so on, in order to facilitate routing of the bit lines (bit0_bk0 to bit31_bk3) and to decrease capacitances seen at the bit lines (bit0_bk0 to bit31_bk3).
However, when thirty-two of the memory cells 13 that correspond to the bit lines (bit0_bkA to bit31_bkA) and to the word line (ctr_B), are selected to have data stored therein be read, one-hundred-and-twenty-eight of the memory cells 13, that correspond to the word line (ctr_B), may charge or discharge the bit lines (bit0_bk0 to bkt31_bk3), where 0≦B≦255. This results in a relatively large amount of unnecessary power consumption.